Integrated circuit (IC) design typically involves several stages, each using a different tool of suite of tools. An IC designer typically writes code in one of several programming languages. Concurrent with the code-writing process is simulation, in which the designer runs a simulator tool to test the design, using the program code as input. As simulation reveals problems, the designer edits the code to fix problems, and simulates again. After simulation, a synthesizer translates the code into a logical representation of an IC. Other IC tools then transform this logical representation into a physical IC, in the form of a Field Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), or custom silicon IC.
Several types of programming languages are available to an IC designer. One family of languages can be described as Hardware Design Languages (HDL), also known as Register Transfer Languages (RTLs). Commonly known RTLs include Verilog and VHDL. RTLs are considered to be “low-level” because they describe hardware-specific features such as timing and parallelism. Another choice for IC design includes languages such as C and C++ (and variants thereof) that were traditionally used to develop software rather than hardware. These software languages allow the designer to write code at a much higher level of abstraction, which can increase designer productivity.
However, as many prevalent simulation and synthesis tools use HDL as input, rather than C/C++, an IC designer may choose to write code in C/C++ and translate the code into HDL. The translation can be done manually, automatically, or using a combination of both techniques. Further, simulation and synthesis tools using HDL as input often may not offer robust debugging capabilities to allow a hardware designer to easily and effectively debug a hardware design. For example, such simulation and synthesis tools typically allow a hardware designer or tester to examine data dumped and extracted from the simulation and synthesis tool, but they typically do not allow for more granular or detailed debugging operations and testing of graphics hardware designs.